Modern day integrated chips contain millions of semiconductor devices. The semiconductor devices are electrically interconnected by way of back-end-of-the-line metal interconnect layers that are formed above the devices on an integrated chip. A typical integrated chip comprises a plurality of back-end-of-the-line metal interconnect layers including different sized metal wires vertically coupled together with metal contacts (i.e., vias).
Back-end-of-the-line metal interconnect layers are often formed using a dual damascene process. In a dual damascene process, a dielectric material is deposited (e.g., low k dielectric, ultra low k dielectric) onto the surface of a semiconductor substrate. The dielectric material is then selectively etched to form cavities in the dielectric material for a via layer and for an adjoining metal layer. In a typical via-first dual damascene process, a via hole is first etched in the dielectric material and then a metal line trench is formed on top of the via hole. After the via and trench are formed, a diffusion barrier layer and a seed layer are deposited within the cavities. An electro chemical platting process is then used to fill the via and metal trenches with metal (e.g., copper) at the same time. Finally, the surface of the substrate is planarized using a chemical mechanical polishing process to remove any excess metal.